The present invention relates to electronic data processing (EDP) systems, and more particularly to EDP systems which have multiple processors, each processor having its own cache memory, interconnected by multiple interconnections, e.g. buses.
Cache memories were originally added to uniprocessor systems in order to increase memory access speed. Without cache memories, every memory access, either READ or WRITE, involved main memory. Typically main memory was distantly located, and also was relatively slow in operation. This meant that a number of processor cycles were required in order to access data stored at a main memory address. It was found that the number of processor cycles required for an access could be reduced by transferring the data of some main memory addresses to a cache memory that is closer to the uniprocessor and faster at READING and WRITING the data than main memory. When a transaction involving encached data is completed, the resulting data is typically stored in the cache memory again and also is eventually copied back to the corresponding address locations in main memory. For proper system operation some type of record is kept to indicate at the end of an operation whether the location for the resulting data corresponding to an address is in cache memory or in main memory.
A multiple processor system that has a cache memory associated with each of its processors has an even more complex data problem. In multiple processor systems, each cache may contain data associated with a main memory address, and each processor may process the data for that address and store the results in its respective cache. Thus, unless something in the EDP system prevents it, it is possible that many different data values will exist among the multiple caches for a single address. This possible inconsistency among corresponding address locations is referred to in the art as the cache coherency problem.
One solution to the cache coherency problem requires the main memory to record the location of each encached copy of data associated with a main memory address. When any encached copy is modified, the results are stored in the cache of the processor performing the processing, copied through to the corresponding address in main memory, and then copied to each additional cache that also has data associated with the main memory address. It is up to the EDP system to provide a cache data protocol for the processing of the data associated with each address so that each of the processors always processes current, coherent data. The copy back process works quite well for two processor systems; however, as the number of processors increases, the interconnect sub-system tends to become overloaded by the frequent copying back of information to main memory and the frequent updating of all of the encached copies of the information. In such a system, the gains in processing power provided by multiple processors may be negated by the overloading of the system interconnect by update messages to the processor caches.
One approach to preventing the cache messages from overloading and bogging down the common system interconnect is to provide a separate cache management subsystem, including a separate cache interconnect. Such a separate cache interconnect connecting to each cache memory, however, is the equivalent of a second system interconnect in speed and data requirements. So this approach adds a non-standard cache interconnect that is roughly equivalent to common system interconnect. Such a cache interconnect would require considerable software and hardware investments to upgrade existing platforms or to manufacture a completely new software and hardware platform.
A second approach to preventing the cache messages from overloading the common interconnect is to provide multiple system interconnects, e.g. multiple parallel buses to a common memory. By spreading the data traffic among multiple parallel buses, the traffic on each bus could be reduced such that the copying back, or similar operation, of resulting data would not cause an overload. However, such a system architecture may require as many parallel system buses as there are processors with caches. Since typical standard system bus architectures have one or two system buses, such architectures could not be readily extended to systems with five processors or more without incurring expensive custom hardware components and considerably more complex memory architectures.
Thus, there is an unfulfilled need for a method and apparatus for interconnecting a number of processors with a like number of caches which maintains data coherency and yet may be effectively used within existing system hardware and back plane designs.
It is an object of the present invention to provide a method and apparatus that ensures coherency of the data in each cache of a multiple bus interconnection system.
It is a further object of the present invention to provide an apparatus that ensures coherency of encached data which is extensible within existing system interconnect architectures.